Voltage change reflecting delay calculation method, and voltage change reflecting delay calculation system

ABSTRACT

A method for designing a semiconductor integrated circuit is proposed. The semiconductor integrated circuit includes power supply terminals each formed out of an area bump and signal terminals. Distance from the logic cell or the module to a power supply area bump closest thereto is obtained for the logic cell or the module. Further, a power supply voltage which is estimated to be actually applied to the logic cell or the module is obtained based on the obtained distance and a power supply voltage applied to the power supply area bump. Finally, a delay is calculated based on the estimated power supply voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No.2002-075481, filed on Mar.19, 2002, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a technology of calculate adelay in designing a semiconductor integrated circuit by estimating achange in a power supply voltage which is estimated to be actuallyapplied to a logic cell or a module based on a distance to a powersupply area bump closest to the logic cell or the module and a powersupply voltage applied to the power supply area bump for each logic cellor module. 2. Description of the Related Art

[0004] Generally, a voltage applied to each logic cell in asemiconductor integrated circuit is lower than a voltage applied to apower supply source, depending on the position at which the logic cellis arranged, the distance of the logic cell from the power supply sourceor the like. This is caused by voltage change which derives from awiring parasitic element such as a resistance or a capacitance. Themagnitude of the voltage to be applied to each logic cell is one of theimportant factors which influence the delay of the cell. Therefore, itis important to design the semiconductor integrated circuit not byuniformly applying the voltage of the power supply source to all logiccells but by reflecting the influence of the voltage change of eachlogic cell.

[0005] If the semiconductor integrated circuit is designed withoutconsideration to the influence of voltage change, the error between adelay which is obtained by calculation in a design phase and a measureddelay in an actual circuit becomes greater, which causes disadvantagessuch as the need to redesign the semiconductor integrated circuit. If asemiconductor integrated circuit is to be designed under a design ruleof less than 0.5 μm, called “deep submicron”, in particular, it isnecessary to fully consider the influence of the voltage change of eachlogic cell.

[0006] Two methods are conventionally known for calculating a delaywhich reflects the influence of the voltage change of each logic cell asfollows. The first method is to calculate a delay by extracting aparasitic element of a power supply wiring which connects a power supplyterminal to a logic circuit using layout data and process parameters andby multiplying delay time by a power supply voltage or currentcoefficient which is calculated based on the extracted parasiticelement. The second method is to obtain a delay by applying a maximum orminimum voltage change for an entire chip.

[0007] The first method, however, has the following disadvantages. Ittakes a lot of time to perform calculation, design TAT (Turn AroundTime) considerably increases, and it is, therefore, impractical to applythe first method to actual circuit design. The second method has thefollowing disadvantages. If the maximum voltage change is used, thesemiconductor integrated circuit is designed under excessive conditions,making it difficult to converge design steps. If the minimum voltagechange is used, a margin becomes insufficient, with the result that somecircuits malfunction. If so, it takes a long time to analyze themalfunction and yield deteriorates. Therefore, whichever is selected,the maximum or the minimum, design TAT increases.

SUMMARY OF THE INVENTION

[0008] It is an object of this invention to provide a voltage changereflecting delay calculation method and a voltage change reflectingdelay calculation system which can obtain a delay which reflects theinfluence of the voltage change of each logic cell or module whileminimizing an increase in design TAT.

[0009] According to the present invention, in designing a semiconductorintegrated circuit which includes power supply terminals each formed outof an area bump and signal terminals, a distance from the logic cell orthe module to a power supply area bump closest thereto is obtained foreach logic cell or module, a power supply voltage which is estimated tobe actually applied to the logic cell or the module is obtained based onthe obtained distance and a power supply voltage applied to the powersupply area bump, and a delay according to the estimated power supplyvoltage is obtained.

[0010] According to the above aspect, a change in a power supply voltagewhich is actually applied to a logic cell or module is estimated basedon a distance between the logic cell or the module and a power supplyarea bump. Therefore, it is possible to obtain a delay which reflectsthe influence of the voltage change of each logic cell or module whileminimizing an increase in design TAT.

[0011] These and other objects, features and advantages of the presentinvention are specifically set forth in or will become apparent from thefollowing detailed descriptions of the invention when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a schematic diagram that shows the configuration of avoltage change reflecting delay calculation system for executing avoltage change reflecting delay calculation method in a first embodimentaccording to the present invention,

[0013]FIG. 2 is a flowchart which shows processing procedures for thevoltage change reflecting delay calculation method in the firstembodiment according to the present invention,

[0014]FIG. 3 is a typical view which shows the neighborhood of an areabump to explain the voltage change reflecting delay calculation methodin the first embodiment according to the present invention,

[0015]FIG. 4 is a flowchart which shows procedures for a logic designprocessing to which the voltage change reflecting delay calculationmethod in the first embodiment according to the present invention isapplied,

[0016]FIG. 5 is a flowchart which shows procedures for a physical designprocessing to which the voltage change reflecting delay calculationmethod in the first embodiment according to the present invention isapplied,

[0017]FIG. 6 is a schematic diagram that shows the configuration of avoltage change reflecting delay calculation system for executing avoltage change reflecting delay calculation method in a secondembodiment according to the present invention, and

[0018]FIG. 7 is a flowchart which shows processing procedures for thevoltage change reflecting delay calculation method in the secondembodiment according to the present invention.

DETAILED DESCRIPTIONS

[0019] Embodiments of the present invention will be explainedhereinafter in detail with reference to the accompanying drawings.

[0020]FIG. 1 is a schematic diagram that shows the configuration of avoltage change reflecting delay calculation system for executing avoltage change reflecting delay calculation method in a first embodimentaccording to the present invention. This system includes a cellarrangement position information acquisition section 1, a bump positioninformation acquisition position 2, a cell-bump distance calculator 3, adelay change ratio calculator 4, a delay calculator 5, a library storagesection 6, and a data monitor 7.

[0021] The cell arrangement position information acquisition section 1acquires information on the arrangement position of each logic cell in acircuit in a design tool 8, and stores the acquired information. Thebump position information acquisition section 2 acquires information onthe position of a bump in a circuit in the design tool 8, and stores theacquired information. The cell-bump distance calculator 3 calculates thedistance between each logic cell and an area bump closest to the logiccell for each logic cell based on the logic cell arrangement positioninformation and the power supply area bump position information whichare stored in the cell arrangement position information acquisitionsection 1 and the bump position information acquisition section 2,respectively.

[0022] The delay change ratio calculator 4 calculates a change ratio toa standard delay (“delay change ratio”) based on the distance which iscalculated by the cell-bump distance calculator 3 and a power supplyvoltage applied to the power supply area bump for each logic cell. Thestandard delay is preset as a delay in a standard state and stored inthe library storage section 6. The standard state means a state in whichit is assumed that the same power supply voltage as that of the powersupply area bump is applied to a logic cell. The delay calculator 5calculates a delay based on the delay change ratio which is calculatedby the delay change ratio calculator 4 and the standard delay for eachlogic cell.

[0023] The data monitor 7 transmits a signal to the cell arrangementposition information acquisition section 1 or the bump positioninformation acquisition section 2 in response to a change in a cellarrangement position or a bump position, thereby notifies the section 1or 2 of the change. This is because the cell arrangement position or thebump position is often changed according to an individual processing(logic optimization or physical optimization).

[0024] A method for calculating the delay change ratio P by the delaychange ratio calculator 4 will next be explained. As shown in FIG. 3, aplurality of logic cells (u₁, u₂, . . . and u_(n)) 23, 24 and 25 arearranged along a pair of a power supply voltage-side wiring 21 and aground voltage-side wiring 22, and distances between the logic cells 23,24 and 25 of u₁, u₂ and u_(n) and a power supply-side power supply areabump 26 closest thereto are expressed by d₁, d₂ and d_(n), respectively.Symbol n is a natural number. In addition, if the distance di (where iis a natural number not greater than n) is considered while beingdivided to an x-direction component and a y-direction component in an xycoordinate system, an x-direction distance is expressed by d_(ix), and ay-direction distance is expressed by d_(iy).

[0025] The delay change ratio P is calculated by one of the followingmethods (1) to (4). It is assumed herein that a power supply voltageapplied to the power supply voltage-side power supply area bump 26 is VDand a ground voltage which is applied to a ground voltage-side powersupply area bump 27 is VS. It is also assumed herein that a constantrelated to the calculation of the delay change ratio is α, and theconstants of the x component and the y component related to thecalculation of the delay change ratio are α_(x) and α_(y), respectively.

[0026] (1) Method by using the logic cell u_(i), the distance d_(i)between the logic cell u_(i) and the power supply area bump closestthereto and the constant α,

[0027] According to this method, α is constant irrespective of d_(i).The delay change ratio P is obtained by the following equation.

P=d _(i)×α×(VD−VS)

[0028] (2) Method by using the constant α according to the range of thedistance di between the logic cell ui and the power supply area bumpclosest thereto,

[0029] According to this method, α varies according to the range ofd_(i). For example, if d_(i)>1000, α=1.6; if 1000>d_(i)≧500, α=1.5; andif d_(i)<500, α=1.2. The delay change ratio P is obtained by thefollowing equation.

P=α×(VD−VS)

[0030] (3) Method by using the x-direction distance d_(ix) andy-direction distance d_(iy) between the logic cell u_(i) and the powersupply area bump closest thereto, the x component constant α_(x) and they component constant α_(y),

[0031] According to this method, α_(x) and α_(y) are constantirrespective of d_(ix) and d_(iy), respectively. The delay change ratioP is obtained by the following equation.

P=(d _(ix)×α_(x) +d _(iy)×α_(y))×(VD−VS)

[0032] (4) Method by using the x component constant α_(x) according tothe range of the x-direction distance d_(ix) and the y componentconstant α_(y) according to the range of the y-direction distance d_(iy)between the logic cell u_(i) and the power supply area bump closestthereto,

[0033] According to this method, α_(x) and α_(y) vary according to theranges d_(ix) and d_(iy), respectively. For example, if d_(ix)≧1000,α_(x)=1.6; if 1000>d_(ix)≧500, α_(x)=1.5; and if d_(ix)<500, α_(x)=1.2.In addition, if d_(iy)≧1000, α_(y)=1.7; if 1000>d_(iy)≧500, α_(y)=1.5;and if d_(iy)<500, α_(y)=1.1. The delay change ratio P is obtained bythe following equation.

P=(α_(x),+α_(y))×(VD−VS)

[0034]FIG. 2 is a flow chart which shows processing procedures for thevoltage change reflecting delay calculation method in the firstembodiment according to the present invention. The arrangement positionof each logic cell and the position of each power supply area bump areextracted from after-arrangement layout data 31 (at step S21). Based oninformation on the extracted logic cell arrangement position and theextracted power supply area bump position, the distance d_(i) (which maybe d_(ix) and d_(iy)) between each logic cell and the power supply areabump closest thereto is calculated for each logic cell (at step S22). Tocalculate the distance and to select the closest power supply area bump,an ordinary two-dimensional coordinate system method using xycoordinates of each logic cell and each power supply area bump isavailable.

[0035] The power supply voltage VD, the ground voltage VS, the constantssuch as α, α_(x) and α_(y) are received as process parameters 32, andthe delay change ratio P of each logic cell is calculated using thedistance d_(i) or d_(ix) and d_(iy) calculated at the step S22 by one ofthe methods (1) to (4) (at step S23). The standard delay is calculatedfrom the delay calculation library 33, and the delay of each logic cellis calculated using the delay change ratio P calculated at the step S23(at step S24). As a result, a delay 34 which reflects voltage change isobtained for each logic cell.

[0036] The after-arrangement layout data 31 and the process parameters32 are supplied from the design tool 8 in the system shown in FIG. 1. Inaddition, the delay calculation library 33 is stored in the librarystorage section 6 in the system shown in FIG. 1. Further, the delay 34which is obtained by the calculation of the delay at the step S24 issupplied to the design tool 8 and, as will be explained later, used asthe delay of each logic cell in processings performed while using thedelays in the design flow of a semiconductor integrated circuit whichincludes power supply terminals each formed out of an area bump andsignal terminals.

[0037] The reason for limiting the shape of the power supply terminal tothe shape of an area bump is as follows. In a semiconductor integratedcircuit which does not include an area bump, a power supply terminal isarranged around a chip. In a semiconductor integrated circuit whichincludes power supply terminals each formed out of an area bump andsignal terminals, by contrast, power supply area bumps are arranged onthe surface of a chip almost equidistantly. Therefore, an averagedistance from the power supply area bumps to the respective logic cellsis short, so that the accuracy of the calculated values can bemaintained in this embodiment in which the delay is calculated using thedistance from each logic cell to the power supply area bump as aparameter.

[0038] The processings performed while using the delays in the designflow will be explained. The processings include, for example, a layoutprocessing for placement and routing followed by timing driven in aphysical design processing, a timing verification processing after thelayout processing and the like in a design system using a CAD tool. In aaddition, the processings include a logic synthesis optimizationprocessing or the like in a logic design processing.

[0039]FIG. 4 is a flowchart which shows procedures for the logic designprocessing. If a logic design processing starts, an initial logiccircuit synthesis processing is performed for a module (at step S41). Afloor plan processing is then performed (at step S42) and a logic cellarrangement processing is performed (at step S43). Based on the logiccell arrangement position information and the power supply area bumpposition information, the voltage change reflecting delay calculationmethod shown in FIG. 2 is executed by the voltage change reflectingdelay calculation system 41 shown in FIG. 1, to obtain a delay whichreflects the voltage change of each logic cell and to perform a logicoptimization processing using the delay (at step S44). The floor plan,arrangement and logic optimization processings are repeated until theoptimized result meets circuit restrictions. If the optimized resultmeets the circuit restrictions, the logic design processing is finished.

[0040]FIG. 5 is a flowchart which shows procedures for the physicaldesign processing. If a physical design processing starts, a floor planprocessing is performed (at step S51). Using the restriction informationwhich is obtained by a static timing analysis performed by a statictiming analysis tool (STA) 52 based on circuit restrictions 51, a logiccell arrangement processing is performed (at step S52). Based on thelogic cell arrangement position information and the power supply areabump position information, the voltage change reflecting delaycalculation method shown in FIG. 2 is executed by the voltage changereflecting delay calculation system 53 shown in FIG. 1, to obtain adelay which reflects the voltage change of each logic cell. Based on thedelay information thus obtained, the static timing analysis tool 52performs a static timing analysis again.

[0041] Using the restriction information which is newly obtained by thestatic timing analysis, the static timing analysis tool 52 performs aclock tree synthesis processing (at step S53). At this time, the logiccell arrangement position and the power supply area bump position aresometimes changed. The voltage change reflecting delay calculationmethod is executed again by the voltage change reflecting delaycalculation system 53 based on the updated information of the positioninformation, to newly obtain a delay which reflects the voltage changeof each logic cell. Based on the delay information thus obtained, thestatic timing analysis tool 52 performs a static timing analysis again.

[0042] Using the latest restriction information which is obtained by thestatic timing analysis, a timing optimization processing is performed(at step S54). Based on the updated information on the logic cellarrangement position and the power supply area bump position, thevoltage change reflecting delay calculation method is executed again bythe voltage change reflecting delay calculation system 53, to newlyobtain a delay which reflects the voltage change of each logic cell.Based on the delay information thus obtained, the static timing analysistool 52 performs a static timing analysis again.

[0043] Using the latest restriction information obtained by the statictiming analysis, a routing processing is performed (at step S55). Basedon the latest information on the logic cell arrangement position and thepower supply area bump position, the voltage change reflecting delaycalculation method is executed again by the voltage change reflectingdelay calculation system 53, to newly obtain a delay which reflects thevoltage change of each logic cell.

[0044] After the routing processing, if the circuit restrictions are notmet (‘No’ at the step S56), the floor plan processing at the step S51and the following are performed again. If the circuit restrictions aremet (‘Yes’ at the step S56), an RC extraction processing is performed(at step S57). Based on the latest delay obtained by the voltage changereflecting delay calculation system 53, a delay calculation is performed(at step S58). Based on the latest delay obtained by the voltage changereflecting delay calculation system 53, a static timing analysis isperformed (at step S59).

[0045] As a result of the analysis, if the circuit restrictions are notmet (‘No’ at step S60), a timing ECO (Engineering Change Order)processing is performed until the circuit restrictions are met (at stepS61). If the circuit restrictions are met (‘Yes’ at the step S60), thephysical design processing is finished.

[0046] According to the first embodiment, the delay change ratio isobtained based on the distance between each logic cell and the powersupply area bump closest thereto and on the power supply voltage appliedto the voltage area bump, and an actual delay relative to the standarddelay is calculated using the delay change ratio. It is, therefore,possible to obtain the delay of each logic cell which reflects theinfluence of a change in the power supply voltage which is actuallyapplied to the logic cell. At this time, only the two parameters, i.e.,the distance from each logic cell to the power supply area bump and thepower supply voltage of the power supply area bump are employed. It is,therefore, possible to minimize an increase in design TAT.

[0047] According to the first embodiment, a semiconductor integratedcircuit can be designed for each logic cell using a delay according to apower supply voltage. Therefore, the error of the delay of an actualcircuit from the calculated delay which is obtained in the design phasecan be made small and operation faults can be minimized. It is,therefore, possible to improve yield, to decrease fault analysis timeand time required to redesign the circuit and to thereby shorten designTAT.

[0048]FIG. 6 is a schematic diagram that shows a voltage changereflecting delay calculation system for executing voltage changereflecting delay calculation method in a second embodiment according tothe present invention. This system includes a cell arrangement positioninformation acquisition section 1, a bump position informationacquisition section 2, a cell-bump distance calculator 3, a power supplyvoltage calculator 14, a library selector 15, a library database 16 anda data monitor 7. The same constituent elements as those in the firstembodiment are denoted by the same reference symbols, respectively andwill not be explained herein.

[0049] The power supply voltage calculator 14 calculates and obtains apower supply voltage which is actually applied to each logic cell basedon the distance which is calculated by the cell-bump distance calculator3 and on the power supply voltage applied to each power supply areabump, for each logic cell. The library selector 15 selects a librarywhich is used by each logic cell based on the power supply voltage whichis actually applied to the logic cell and which is calculated by thepower supply voltage calculator 14, for each logic cell. The librarydatabase 16 stores a library having information on logic cells whichcorrespond to various power supply voltages and the delays of the logiccells. The library database 16 supplies a necessary library to a designtool based on a select signal which is fed from the library selector 15.

[0050] A method for calculating a power supply voltage V_(ui) by thepower supply voltage calculator 14 will next be explained. The powersupply voltage V_(ui) which is actually applied to each logic cell iscalculated by one of the following methods (5) to (8). It is assumedherein that a change in the power supply voltage which is actuallyapplied to each logic cell relative to the power supply voltage appliedto the power supply area bump is ΔV. It is also assumed herein, that aconstant related to a distance to the power supply voltage is β, and anx component constant and a y component constant related to the distanceto the power supply voltage are β_(x) and β_(y), respectively. Thesymbols d_(i), d_(ix), d_(iy), VD and VS are the same as those explainedin the first embodiment.

[0051] (5) Method by using the logic cell u_(i), the distance d_(i)between the logic cell u_(i) and the power supply area bump closestthereto and the constant β,

[0052] According to this method, β is constant irrespective of d_(i).The power supply voltage V_(ui) of the logical cell is obtained by thefollowing two equations:

ΔV=d _(i)×β×(VD−VS)

V _(ui) =VD+ΔV.

[0053] (6) Method by using the constant β according to the range of thedistance d_(i) between the logic cell u_(i) and the power supply areabump closest thereto,

[0054] According to this method, β varies according to the range ofd_(i). For example, if d_(i)≧1000, β=1.6; if 1000>d_(i)>500, β=1.5; andif d_(i)<500, β=1.2. The power supply voltage V_(ui) is obtained by thefollowing two equations:

ΔV=β×(VD−VS)

V _(ui) =VD+ΔV.

[0055] (7) Method by using the x-direction distance d_(ix) andy-direction distance d_(iy) between the logic cell u_(i) and the powersupply area bump closest thereto, the x component constant β_(x) and they component constant β_(y),

[0056] According to this method, β_(x) and β_(y) are constantirrespective of d_(ix) and d_(iy), respectively. The power supplyvoltage V_(ui) of the logic cell is obtained by the following twoequations:

ΔV=(d_(ix) ×β _(x) +d _(iy)×β_(y))×(VD−VS)

V _(ui) =VD+AV.

[0057] (8) Method by using the x component constant β_(x) according tothe range of the x-direction distance d_(ix) and they component constantβ_(y) according to the range of the y-direction distance d_(iy) betweenthe logic cell u_(i) and the power supply area bump closest thereto,

[0058] According to this method, β_(x) and β_(y) vary according to theranges of d_(ix) and d_(iy), respectively. For example, if d_(ix)>1000,β_(x)=1.6; if 1000>d_(ix)≧500, β_(x)=1.5; and if d_(ix)<500, β_(x)=1.2.In addition, if d_(iy)≧1000, β_(y)=1.7; if 1000>d_(iy)≧500, β_(y)=1.5;and if d_(iy)<500, β_(y)=1.1. The power supply voltage V_(ui) of thelogic cell is obtained by the following two equations:

ΔV=(β_(x)+β_(y))×(VD−VS)

V _(ui) =VD+ΔV.

[0059]FIG. 7 is a flowchart which shows processing procedures for thevoltage change reflecting delay calculation method in the secondembodiment according to the present invention. The arrangement positionof each logic cell and the position of each power supply area bump areextracted from after-arrangement layout data 31 (at step S71). Based oninformation on the extracted logic cell arrangement position and theextracted power supply area bump position, the distance d_(i) (which maybe d_(ix) and d_(iy)) between each logic cell and the power supply areabump closest thereto is calculated for each logic cell (at step S72). Tocalculate the distance and to select the closest power supply area bump,an ordinary two-dimensional coordinate system method using xycoordinates of each logic cell and each power supply area bump isavailable.

[0060] The power supply voltage VD, the ground voltage VS, the constantssuch as β, β_(x) and β_(y) are received as process parameters 35, andthe power supply voltage V_(ui) of each logic cell is calculated usingthe distance d_(i) or d_(ix) and d_(iy) calculated at the step S72 byone of the methods (5) to (8) (at step S73). A library which correspondsto the power supply voltage V_(ui) of each logic cell calculated at thestep S73 is selected from a power supply dependent delay library group36 which stores libraries for the power supply voltages of respectivelogic cells used in a circuit (at step S74) As a result, a delay 34which reflects the voltage change of each logic cell is obtained basedon the delay information allocated to the selected library.

[0061] The after-arrangement layout data 31 and the process parameters35 are supplied from the design tool 8 in the system shown in FIG. 6. Inaddition, the power supply dependent delay library group 36 correspondsto the library database 16 shown in FIG. 6. Further, the delay 34 issupplied to the design tool 8 and, similarly to the first embodiment,used as the delay of each logic cell in processings performed whileusing the delays in the design flow of a semiconductor integratedcircuit which includes power supply terminals each formed out of an areabump and signal terminals. Since the processings performed while usingthe delays in the design flow are the same as those explained in thefirst embodiment, they will not be explained herein.

[0062] According to the second embodiment, the power supply voltage ofeach logic cell is obtained based on the distance between the logic celland the power supply area bump closest thereto and the power supplyvoltage applied to the power supply area bump. To select a library whichcorresponds to the power supply voltage thus obtained, it is possible toobtain the delay of each logic cell which reflects the influence of achange in a power supply voltage which is actually applied to the logiccell while minimizing an increase in design TAT.

[0063] The present invention explained so far is not limited to theembodiments but various changes and modifications can be made. Inaddition, the present invention may be applied to, for example, theinitial logic circuit synthesis in the logic design processing shown inFIG. 4. In that case, the logic cell may be changed to a module in theabove explanation.

[0064] According to the present invention, a change in the power supplyvoltage which is actually applied to each logic cell or module isestimated based on the distance between the logic cell or the module andthe power supply area bump. It is, therefore, possible to obtain a delaywhich reflects the influence of voltage change for each logic cell ormodule while minimizing an increase in design TAT.

[0065] Although the invention has been described with respect to aspecific embodiment for a complete and clear disclosure, the appendedclaims are not to be thus limited but are to be construed as embodyingall modifications and alternative constructions that may occur to oneskilled in the art which fairly fall within the basic teaching hereinset forth.

What is claimed is:
 1. A voltage change reflecting delay calculationmethod for calculating a delay which is caused by a change in a powersupply voltage of each logic cell or module which constitutes asemiconductor integrated circuit which includes power supply terminalseach formed out of an area bump and signal terminals, the methodcomprising: an arrangement position information acquisition step ofacquiring arrangement position information on the logic cell or themodule from design data; a bump position information acquisition step ofacquiring arrangement position information on each power supply areabump from the design data; a distance calculation step of calculating adistance from the logic cell or the module to the closest power supplyarea bump for each logic cell or module, based on the arrangementposition information on the logic cell or the module acquired at thearrangement position information acquisition step, and on thearrangement position information on the power supply area bump acquiredat the bump position information acquisition step; a delay change ratiocalculation step of calculating a change ratio of a delay to a standarddelay which is preset as the delay in a standard state for the logiccell or the module, based on the distance obtained at the distancecalculation step and on a power supply voltage applied to the powersupply area bump; and a delay calculation step of calculating the delaywhich reflects a power supply voltage which is estimated to be actuallyapplied to the logic cell or the module, for the logic cell or themodule, based on the change ratio which is obtained at the delay changeratio calculation step and on the standard delay.
 2. The voltage changereflecting delay calculation method according to claim 1, wherein at thedelay change ratio calculation step, a coefficient that corresponds to arange of the distance obtained at the distance calculation step isselected from a preset coefficient group, and the change ratio iscalculated for the logic cell or the module based on the coefficient andthe power supply voltage applied to the power supply area bump.
 3. Thevoltage change reflecting delay calculation method according to claim 1,wherein at the distance calculation step, the distance from the logiccell or the module to the closest power supply area bump is calculatedby separating the distance into an x-direction component and ay-direction component in an xy coordinate system, for the logic cell orthe module, and at the delay change ratio calculation step, the changeratio is calculated for the logic cell or the module based on thex-direction component distance and the y-direction component distanceobtained at the distance calculation step, and on the power supplyvoltage applied to the power supply area bump.
 4. The voltage changereflecting delay calculation method according to claim 1, wherein at thedistance calculation step, the distance from the logic cell or themodule to the closest power supply area bump is calculated by separatingthe distance into an x-direction component and a y-direction componentin an xy coordinate system, for the logic cell or the module, and at thedelay change ratio calculation step, a coefficient that corresponds to arange of the x-direction component distance and a coefficient thatcorresponds to a range of the y-direction component distance obtained atthe distance calculation step are selected from a preset x-directioncomponent coefficient group and a preset y-direction componentcoefficient group, respectively, and the change ratio is calculated forthe logic cell or the module based on the x-direction componentcoefficient, the y-direction component coefficient and the power supplyvoltage applied to the power supply area bump.
 5. A voltage changereflecting delay calculation method for calculating a delay which iscaused by a change in a power supply voltage of each logic cell ormodule which constitutes a semiconductor integrated circuit whichincludes power supply terminals each formed out of an area bump andsignal terminals, the method comprising: an arrangement positioninformation acquisition step of acquiring arrangement positioninformation on the logic cell or the module from design data; a bumpposition information acquisition step of acquiring arrangement positioninformation on each power supply area bump from the design data; adistance calculation step of calculating a distance from the logic cellor the module to the closest power supply area bump for the logic cellor the module, based on the arrangement position information on thelogic cell or the module acquired at the arrangement positioninformation acquisition step, and on the arrangement positioninformation on the power supply area bump acquired at the bump positioninformation acquisition step; a power supply voltage calculation step ofcalculating a power supply voltage which is estimated to be actuallyapplied to the logic cell or the module, for the logic cell or themodule, based on the distance obtained at the distance calculation stepand on a power supply voltage applied to the power supply area bump; anda library selection step of selecting a library of delays thatcorresponds to the power supply voltage obtained at the power supplyvoltage calculation step.
 6. The voltage change reflecting delaycalculation method according to claim 5, wherein at the power supplyvoltage calculation step, a coefficient that corresponds to a range ofthe distance obtained at the distance calculation step is selected froma preset coefficient group, and the power supply voltage which isestimated to be actually applied to the logic cell or the module iscalculated for the logic cell or the module based on the coefficient andthe power supply voltage applied to the power supply area bump.
 7. Thevoltage change reflecting delay calculation method according to claim 5,wherein at the distance calculation step, the distance from the logiccell or the module to the closest power supply area bump is calculatedby separating the distance into an x-direction component and ay-direction component in an xy coordinate system, for the logic cell orthe module, and at the power supply voltage calculation step, the powersupply voltage which is estimated to be actually applied to the logiccell or the module is calculated for the logic cell or the module basedon the x-direction component distance and the y-direction componentdistance obtained at the distance calculation step, and on the powersupply voltage applied to the power supply area bump.
 8. The voltagechange reflecting delay calculation method according to claim 5, whereinat the distance calculation step, the distance from the logic cell orthe module to the closest power supply area bump is calculated byseparating the distance into an x-direction component and a y-directioncomponent in an xy coordinate system, for the logic cell or the module,and at the power supply voltage calculation step, a coefficient thatcorresponds to a range of the x-direction component distance and acoefficient that corresponds to a range of the y-directioncomponent-distance obtained at the distance calculation step areselected from a preset x-direction component coefficient group and apreset y-direction component coefficient group, respectively, and thepower supply voltage which is estimated to be actually applied to thelogic cell or the module is calculated for the logic cell or the modulebased on the x-direction component coefficient, the y-directioncomponent coefficient and the power supply voltage applied to the powersupply area bump.
 9. A voltage change reflecting delay calculationsystem which calculates a delay which is caused by a change in a powersupply voltage of each logic cell or module which constitutes asemiconductor integrated circuit which includes power supply terminalseach formed out of an area bump and signal terminals, the systemcomprising: an arrangement position information acquisition unit whichacquires and stores arrangement position information on the logic cellor the module from design data; a bump position information acquisitionunit which acquires and stores arrangement position information on eachpower supply area bump from the design data; a distance calculation unitwhich calculates a distance from the logic cell or the module to theclosest power supply area bump for the logic cell or the module, basedon the arrangement position information on the logic cell or the moduleacquired by the arrangement position information acquisition unit, andon the arrangement position information on the power supply area bumpacquired by the bump position information acquisition unit; a librarystorage unit which prepares a library which stores a standard delaywhich is preset as a delay in a standard state; a delay change ratiocalculation unit which calculates a change ratio of a delay to thestandard delay for the logic cell or the module, based on the distancewhich is calculated by the distance calculation unit and on a powersupply voltage applied to the power supply area bump; a delaycalculation unit which calculates the delay which reflects a powersupply voltage which is estimated to be actually applied to the logiccell or the module, for the logic cell or the module, based on thechange ratio which is calculated by the delay change ratio calculationunit and on the standard delay; and a data monitoring unit whichnotifies the arrangement position information acquisition unit and thebump position information acquisition unit that an arrangement positionof the logic cell or the module or the arrangement position of the powersupply area bump in the design data is changed.
 10. The voltage changereflecting delay calculation system according to claim 9, wherein thedelay change ratio calculation unit selects a coefficient thatcorresponds to a range of the distance which is calculated by thedistance calculation unit from a preset coefficient group, andcalculates the change ratio for the logic cell or the module based onthe coefficient and the power supply voltage applied to the power supplyarea bump.
 11. The voltage change reflecting delay calculation systemaccording to claim 9, wherein the distance calculation unit calculatesthe distance from the logic cell or the module to the closest powersupply area bump by separating the distance into an x-directioncomponent and a y-direction component in an xy coordinate system, forthe logic cell or the module, and the delay change ratio calculationunit calculates the change ratio for the logic cell or the module basedon the x-direction component distance and the y-direction componentdistance which are calculated by the distance calculation unit, and onthe power supply voltage applied to the power supply area bump.
 12. Thevoltage change reflecting delay calculation system according to claim 9,wherein the distance calculation unit calculates the distance from thelogic cell or the module to the closest power supply area bump byseparating the distance into an x-direction component and a y-directioncomponent in an xy coordinate system, for the logic cell or the module,and the delay change ratio calculation unit selects a coefficient thatcorresponds to a range of the x-direction component distance and acoefficient that corresponds to a range of the y-direction componentdistance which are calculated by the distance calculation unit from apreset x-direction component coefficient group and a preset y-directioncomponent coefficient group, respectively, and calculates the changeratio for the logic cell or the module based on the x-directioncomponent coefficient, the y-direction component coefficient and thepower supply voltage applied to the power supply area bump.
 13. Avoltage change reflecting delay calculation system which calculates adelay which is caused by a change in a power supply voltage of eachlogic cell or module which constitutes a semiconductor integratedcircuit which includes power supply terminals each formed out of an areabump and signal terminals, the system comprising: an arrangementposition information acquisition unit which acquires and storesarrangement position information on the logic cell or the module fromdesign data; a bump position information acquisition unit which acquiresand stores arrangement position information on each power supply areabump from the design data; a distance calculation unit which calculatesa distance from the logic cell or the module to the closest power supplyarea bump for the logic cell or the module, based on the arrangementposition information on the logic cell or the module acquired by thearrangement position information acquisition unit, and on thearrangement position information on the power supply area bump acquiredby the bump position information acquisition unit; a power supplyvoltage calculation unit which calculates a power supply voltage whichis estimated to be actually applied to the logic cell or the module, forthe logic cell or the module, based on the distance which is calculatedby the distance calculation unit and on a power supply voltage appliedto the power supply area bump; a library database which prepareslibraries each of which stores a delay which is used by a design toolfor each power supply voltage; a library selection unit which suppliesone of the libraries which corresponds to the power supply voltage whichis calculated by the power supply voltage calculation unit, to thedesign data from the library database, for the logic cell or the module;and a data monitoring unit which notifies the arrangement positioninformation acquisition unit or the bump position informationacquisition unit that an arrangement position of the logic cell or themodule or the arrangement position of the power supply area bump in thedesign data is changed.
 14. The voltage change reflecting delaycalculation system according to claim 13, wherein the power supplyvoltage calculation unit selects a coefficient that corresponds to arange of the distance which is calculated by the distance calculationunit from a preset coefficient group, and calculates the power supplyvoltage which is estimated to be actually applied to the logic cell orthe module for the logic cell or the module based on the coefficient andthe power supply voltage applied to the power supply area bump.
 15. Thevoltage change reflecting delay calculation system according to claim13, wherein the distance calculation unit calculates the distance fromthe logic cell or the module to the closest power supply area bump byseparating the distance into an x-direction component and a y-directioncomponent in an xy coordinate system, for the logic cell or the module,and the power supply voltage calculation unit calculates the powersupply voltage which is estimated to be actually applied to the logiccell or the module for the logic cell or the module, based on thex-direction component distance and the y-direction component distancewhich are calculated by the distance calculation unit, and on the powersupply voltage applied to the power supply area bump.
 16. The voltagechange reflecting delay calculation system according to claim 13,wherein the distance calculation unit calculates the distance from thelogic cell or the module to the closest power supply area bump byseparating the distance into an x-direction component and a y-directioncomponent in an xy coordinate system, for the logic cell or the module,and the power supply voltage calculation unit selects a coefficient thatcorresponds to a range of the x-direction component distance and acoefficient that corresponds to a range of the y-direction componentdistance which are calculated by the distance calculation unit from apreset x-direction component coefficient group and a preset y-directioncomponent coefficient group, respectively, and calculates the powersupply voltage which is estimated to be actually applied to the logiccell or the module for the logic cell or the module based on thex-direction component coefficient, the y-direction component coefficientand the power supply voltage applied to the power supply area bump. 17.A semiconductor integrated circuit design method for designing asemiconductor integrated circuit, the semiconductor integrated circuitincluding power supply terminals each formed out of an area bump andsignal terminals, wherein a voltage change reflecting delay calculationprocess is applied to thereby perform a layout processing whileperforming a timing driven processing, the voltage change reflectingdelay calculation process being a process for calculating a delay whichis caused by a change in a power supply voltage of each logic cell ormodule which constitutes a semiconductor integrated circuit whichincludes power supply terminals each formed out of an area bump andsignal terminals, the process comprising: an arrangement positioninformation acquisition step of acquiring arrangement positioninformation on the logic cell or the module from design data; a bumpposition information acquisition step of acquiring arrangement positioninformation on each power supply area bump from the design data; adistance calculation step of calculating a distance from the logic cellor the module to the closest power supply area bump for each logic cellor module, based on the arrangement position information on the logiccell or the module acquired at the arrangement position informationacquisition step, and on the arrangement position information on thepower supply area bump acquired at the bump position informationacquisition step; a delay change ratio calculation step of calculating achange ratio of a delay to a standard delay which is preset as the delayin a standard state for the logic cell or the module, based on thedistance obtained at the distance calculation step and on a power supplyvoltage applied to the power supply area bump; and a delay calculationstep of calculating the delay which reflects a power supply voltagewhich is estimated to be actually applied to the logic cell or themodule, for the logic cell or the module, based on the change ratiowhich is obtained at the delay change ratio calculation step and on thestandard delay.
 18. A semiconductor integrated circuit design method fordesigning a semiconductor integrated circuit, the semiconductorintegrated circuit including power supply terminals each formed out ofan area bump and signal terminals, wherein a voltage change reflectingdelay calculation process is applied to thereby perform a layoutprocessing while performing a timing driven processing, the voltagechange reflecting delay calculation process being a process forcalculating a delay which is caused by a change in a power supplyvoltage of each logic cell or module which constitutes a semiconductorintegrated circuit which includes power supply terminals each formed outof an area bump and signal terminals, the process comprising: anarrangement position information acquisition step of acquiringarrangement position information on the logic cell or the module fromdesign data; a bump position information acquisition step of acquiringarrangement position information on each power supply area bump from thedesign data; a distance calculation step of calculating a distance fromthe logic cell or the module to the closest power supply area bump forthe logic cell or the module, based on the arrangement positioninformation on the logic cell or the module acquired at the arrangementposition information acquisition step, and on the arrangement positioninformation on the power supply area bump acquired at the bump positioninformation acquisition step; a power supply voltage calculation step ofcalculating a power supply voltage which is estimated to be actuallyapplied to the logic cell or the module, for the logic cell or themodule, based on the distance obtained at the distance calculation stepand on a power supply voltage applied to the power supply area bump; anda library selection step of selecting a library of delays thatcorresponds to the power supply voltage obtained at the power supplyvoltage calculation step.
 19. A semiconductor integrated circuit designmethod for designing a semiconductor integrated circuit, thesemiconductor integrated circuit including power supply terminals eachformed out of an area bump and signal terminals, the method comprising avoltage change reflecting delay calculation process that is performedafter a layout processing to perform timing verification, the voltagechange reflecting delay calculation process being a process forcalculating a delay which is caused by a change in a power supplyvoltage of each logic cell or module which constitutes a semiconductorintegrated circuit which includes power supply terminals each formed outof an area bump and signal terminals, the process comprising: anarrangement position information acquisition step of acquiringarrangement position information on the logic cell or the module fromdesign data; a bump position information acquisition step of acquiringarrangement position information on each power supply area bump from thedesign data; a distance calculation step of calculating a distance fromthe logic cell or the module to the closest power supply area bump foreach logic cell or module, based on the arrangement position informationon the logic cell or the module acquired at the arrangement positioninformation acquisition step, and on the arrangement positioninformation on the power supply area bump acquired at the bump positioninformation acquisition step; a delay change ratio calculation step ofcalculating a change ratio of a delay to a standard delay which ispreset as the delay in a standard state for the logic cell or themodule, based on the distance obtained at the distance calculation stepand on a power supply voltage applied to the power supply area bump; anda delay calculation step of calculating the delay which reflects a powersupply voltage which is estimated to be actually applied to the logiccell or the module, for the logic cell or the module, based on thechange ratio which is obtained at the delay change ratio calculationstep and on the standard delay.
 20. A semiconductor integrated circuitdesign method for designing a semiconductor integrated circuit, thesemiconductor integrated circuit including power supply terminals eachformed out of an area bump and signal terminals, the method comprising avoltage change reflecting delay calculation process that is performedafter a layout processing to perform timing verification, the voltagechange reflecting delay calculation process being a process forcalculating a delay which is caused by a change in a power supplyvoltage of each logic cell or module which constitutes a semiconductorintegrated circuit which includes power supply terminals each formed outof an area bump and signal terminals, the process comprising: anarrangement position information acquisition step of acquiringarrangement position information on the logic cell or the module fromdesign data; a bump position information acquisition step of acquiringarrangement position information on each power supply area bump from thedesign data; a distance calculation step of calculating a distance fromthe logic cell or the module to the closest power supply area bump forthe logic cell or the module, based on the arrangement positioninformation on the logic cell or the module acquired at the arrangementposition information acquisition step, and on the arrangement positioninformation on the power supply area bump acquired at the bump positioninformation acquisition step; a power supply voltage calculation step ofcalculating a power supply voltage which is estimated to be actuallyapplied to the logic cell or the module, for the logic cell or themodule, based on the distance obtained at the distance calculation stepand on a power supply voltage applied to the power supply area bump; anda library selection step of selecting a library of delays thatcorresponds to the power supply voltage obtained at the power supplyvoltage calculation step.
 21. A semiconductor integrated circuit designmethod for designing a semiconductor integrated circuit, thesemiconductor integrated circuit including power supply terminals eachformed out of an area bump and signal terminals, wherein a voltagechange reflecting delay calculation process is applied to there byperform floor plan or placement, and a logic optimization processingwhich feeds back information on the floor plan or the placement andwhich optimizes logic is performed, the voltage change reflecting delaycalculation process being a process for calculating a delay which iscaused by a change in a power supply voltage of each logic cell ormodule which constitutes a semiconductor integrated circuit whichincludes power supply terminals each formed out of an area bump andsignal terminals, the process comprising: an arrangement positioninformation acquisition step of acquiring arrangement positioninformation on the logic cell or the module from design data; a bumpposition information acquisition step of acquiring arrangement positioninformation on each power supply area bump from the design data; adistance calculation step of calculating a distance from the logic cellor the module to the closest power supply area bump for each logic cellor module, based on the arrangement position information on the logiccell or the module acquired at the arrangement position informationacquisition step, and on the arrangement position information on thepower supply area bump acquired at the bump position informationacquisition step; a delay change ratio calculation step of calculating achange ratio of a delay to a standard delay which is preset as the delayin a standard state for the logic cell or the module, based on thedistance obtained at the distance calculation step and on a power supplyvoltage applied to the power supply area bump; and a delay calculationstep of calculating the delay which reflects a power supply voltagewhich is estimated to be actually applied to the logic cell or themodule, for the logic cell or the module, based on the change ratiowhich is obtained at the delay change ratio calculation step and on thestandard delay.
 22. A semiconductor integrated circuit design method fordesigning a semiconductor integrated circuit, the semiconductorintegrated circuit including power supply terminals each formed out ofan area bump and signal terminals, wherein a voltage change reflectingdelay calculation process is applied to thereby perform floor plan orplacement, and a logic optimization processing which feeds backinformation on the floor plan or the placement and which optimizes logicis performed, the voltage change reflecting delay calculation processbeing a process for calculating a delay which is caused by a change in apower supply voltage of each logic cell or module which constitutes asemiconductor integrated circuit which includes power supply terminalseach formed out of an area bump and signal terminals, the processcomprising: an arrangement position information acquisition step ofacquiring arrangement position information on the logic cell or themodule from design data; a bump position information acquisition step ofacquiring arrangement position information on each power supply areabump from the design data; a distance calculation step of calculating adistance from the logic cell or the module to the closest power supplyarea bump for the logic cell or the module, based on the arrangementposition information on the logic cell or the module acquired at thearrangement position information acquisition step, and on thearrangement position information on the power supply area bump acquiredat the bump position information acquisition step; a power supplyvoltage calculation step of calculating a power supply voltage which isestimated to be actually applied to the logic cell or the module, forthe logic cell or the module, based on the distance obtained at thedistance calculation step and on a power supply voltage applied to thepower supply area bump; and a library selection step of selecting alibrary of delays that corresponds to the power supply voltage obtainedat the power supply voltage calculation step.
 23. A power supply voltagecalculation method for calculating a power supply voltage of each logiccell or module which constitutes a semiconductor integrated circuitwhich includes power supply terminals each formed out of an area bumpand signal terminals, the method comprising: an arrangement positioninformation acquisition step of acquiring arrangement positioninformation on the logic cell or the module from design data; a bumpposition information acquisition step of acquiring arrangement positioninformation on each power supply area bump from the design data; adistance calculation step of calculating a distance from the logic cellor the module to the closest power supply area bump for the logic cellor the module, based on the arrangement position information on thelogic cell or the module acquired at the arrangement positioninformation acquisition step, and on the arrangement positioninformation on the power supply area bump acquired at the bump positioninformation acquisition step; and a power supply voltage calculationstep of calculating a power supply voltage which is estimated to beactually applied to the logic cell or the module, for the logic cell orthe module, based on the distance obtained at the distance calculationstep and on a power supply voltage applied to the power supply areabump.
 24. The power supply voltage calculation method according to claim23, wherein at the power supply voltage calculation step, a coefficientthat corresponds to a range of the distance obtained at the distancecalculation step is selected from a preset coefficient group, and thepower supply voltage which is estimated to be actually applied to thelogic cell or the module is calculated for the logic cell or the modulebased on the coefficient and the power supply voltage applied to thepower supply area bump.
 25. The power supply voltage calculation methodaccording to claim 23, wherein at the distance calculation step, thedistance from the logic cell or the module to the closest power supplyarea bump is calculated by separating the distance into an x-directioncomponent and a y-direction component in an xy coordinate system, forthe logic cell or the module, and at the power supply voltagecalculation step, the power supply voltage which is estimated to beactually applied to the logic cell or the module is calculated for thelogic cell or the module based on the x-direction component distance andthe y-direction component distance obtained at the distance calculationstep, and on the power supply voltage applied to the power supply areabump.
 26. The power supply voltage calculation method according to claim23, wherein at the distance calculation step, the distance from thelogic cell or the module to the closest power supply area bump iscalculated by separating the distance into an x-direction component anda y-direction component in an xy coordinate system, for the logic cellor the module, and at the power supply voltage calculation step, acoefficient that corresponds to a range of the x-direction componentdistance and a coefficient that corresponds to a range of they-direction component distance obtained at the distance calculation stepare selected from a preset x-direction component coefficient group and apreset y-direction component coefficient group, respectively, and thepower supply voltage which is estimated to be actually applied to thelogic cell or the module is calculated for the logic cell or the modulebased on the x-direction component coefficient, the y-directioncomponent coefficient and the power supply voltage applied to the powersupply area bump.